Disabling the clock signal to the registers in a integrated circuit when they are not in use in a digital synchronous design reduces the active power of the circuit. This clock gating may be implemented in Resistor-Transistor Logic (RTL) by the designer using knowledge of the design's activity. When the data to a register is gated by an enable signal, the design can be converted into a alternative design where the enable signal could be used to gate the clock to the register. This reduces register active power. This process typically receives a RTL design and modifies it to produce a better design for the integrated circuit in power consumption.
Typically clock gates are inserted into an integrated circuit design to save dynamic power on banks of similar registers. These clock gates are typically inserted during synthesis when no placement information is available. Often during timing driven placement the grouping of sinks under clock gates is not optimal. This suboptimality in the clock gates leads to degraded clock tree synthesis quality in clock wire length, insertion delay and clock tree divergence.
FIG. 1 illustrates this idea of converting data gating to clock gating. FIG. 1 illustrates a data gated register circuit 110 and the corresponding clock gated register circuit 150. Date gated register circuit 110 includes multiplexers 111 to 119 and corresponding registers 121 to 129. Clock signal CLK is supplied to a clock input of each register 121 to 129. A first input of each multiplexer 111 to 119 receives the Q output of the corresponding register 121 to 129. A corresponding data input D0 to Dn is supplied to a second input of each multiplexer 111 to 119. An enable signal EN controls the selection input of each multiplexer 111 to 119. The output of each multiplexer 111 to 119 supplies the data input D of the corresponding register 121 to 129. On a first digital state of signal EN, each multiplexer 111 and 119 selects the Q output of the corresponding register. Upon the next pulse of clock signal CLK, this selected signal is supplied to the data input D of each data register 121 to 129. The stores the same contents in each data register 121 to 129 as previously stored. On a second digital state of signal EN opposite to the first state, each multiplexer 111 to 119 selected the corresponding data input D0 to Dn. Upon the next pulse of clock signal CLK, the corresponding data D0 to Dn is stored in data registers 121 to 129.
Clock gated register circuit 150 includes And gate 151 and data registers 161 to 169. A corresponding data input D0 to Dn is supplied to the data input of respective data registers D0 to Dn. Clock signal CLK supplies one input of AND gate 151. Enable signal EN supplies a second input of AND gate 151. When enable signal EN is in the first digital state data registers 161 to 169 are not clocked because AND gate 151 does not pass clock signal CLK to the respective data inputs. Thus the data stored in data registers 161 to 169 is unchanged. When enable signal EN is the in the second digital state AND gate 151 passes the clock signal CLK to the respective clock inputs of data registers 161 to 169. Accordingly, upon the next pulse of clock signal CLK each data register 161 to 169 stores the corresponding data signal.
As shown in the above description data gated register circuit 110 and clock gated register circuit 150 operate similarly relative to the data and clock inputs. These circuits differ because active clock pulses from clock signal CLK are supplied to the data registers only during an active enable EN in clock gated register circuit 150 rather than being continuously supplied as in data gated register circuit 110. Assuming that enable signal EN has an active duty cycle of less than 100%, clock gated register circuit 150 consumes less electric power than data gated register circuit 110.